Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-08-18
2001-01-16
Bragdon, Reginald G. (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
06175895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cache enabling architecture in which information at an output and/or input of a storage reading and/or writing device may be cached. The cache enabling architecture may for example be implemented in a computer system to which the storage reading and/or writing device is connected. Typically the connection is done via a data bus.
2. Background of the Invention
Caching information from storage devices is a known technology. More specially and as examples many solutions are known to cache Random Access Memory, hard disk drive devices and other mass storage devices. These memory devices are of common use in or in combination with computers. The requirements to cache a memory device are basically to provide a faster memory in which information may be accessed more efficiently than in the memory device, and to copy determined information from the memory device to the faster memory or vice versa. The determined information may for example be information which is most likely to be needed or most frequently needed. The copying and an identification of the determined information among information contained in the memory device (or in the faster memory) is performed by a cache processor. The cache processor may for example be a software program which runs on a computer. Caching thus improves the overall performance of information processing systems such as a microprocessor processing information stored in a RAM, or a computer processing information stored on a mass storage device peripheral.
Computers typically are used with peripherals such as magnetic and/or optical storage devices. These storage devices are connected directly or indirectly to a data bus. A microprocessor conducts information exchanges over the data bus between devices connected to this data bus. The performance in terms of access times to information stored on the storage devices varies depending on the nature of the storage devices. For example a performance of a magnetic hard disk drive device may be substantially greater than a performance of an optical disk device. It is known to cache an optical disk device using a magnetic disk drive device as faster memory.
In one implementation of caching a cache processor performs the caching using a direct link between the optical disk device and the hard disk drive device over which information is exchanged. The direct link is required because there is no other way to exchange information between the optical disk device and the magnetic hard disk device without involving the microprocessor and thus substantially slowing down the computer. On the other hand the direct link is a piece of hardware which does not belong to a standard computer equipment and which thus may add to the costs of producing a computer equipped with storage device peripherals.
Recent computer hardware comprises a data bus over which two peripherals may exchange data without significantly interfering with other peripheral connected to the data bus. This means that the microprocessor, which is also known as central processing unit, may perform other tasks than conducting information exchange between the two peripherals. For example, the microprocessor may process data stored in a RAM. The data bus may for example be based on a IEEE 1394 bus.
SUMMARY OF THE INVENTION
It is an object of the present invention to find a solution in which an optical storage device peripheral may be cached using another storage device peripheral but eliminating the need for an own direct link between the two peripherals. The solution should as much as possible make use of an existing computer hardware.
According to the present invention a solution to the above mentioned problem is found in a cache enabling architecture for caching information at an output and/or input of an optical storage reading and/or writing device, comprising at least a mass writing and reading device, based on a magnetical hard disk drive, a data bus to which the mass writing and reading device is indirectly or directly connected and through which instructions sent from further devices other than the optical storage device, reach the mass writing and reading device, and a caching processor to cache the information using the mass writing and reading device. The caching processor is directly connected to the mass writing and reading device. The output and/or input of the optical storage reading and/or writing device and the caching processor are connected through the data bus, so as to directly exchange the information between the output and/or input and the caching processor.
According to the present invention another solution to the above mentioned problem is found in a magnetic hard disk drive device for use in a computer system. The computer system comprises at least a central processing unit, an optical storage reading and/or writing device and a data bus, the central processing unit and the optical storage reading and/or writing device being indirectly or directly connected to the data bus. The magnetic hard disk drive device further comprises a connection circuitry for connecting the magnetic hard disk drive device to the data bus, and a caching processor which receives from the databus requests for reading and/or writing information intended for the optical storage reading and/or writing device and conducts information exchange between the magnetic hard disk drive device and the optical storage reading and/or writing device over the data bus such as to cache the optical storage reading and/or writing device.
REFERENCES:
patent: 5218685 (1993-06-01), Jones
patent: 5806085 (1998-09-01), Berliner
patent: 5884093 (1999-03-01), Berenguel et al.
patent: 44 22 786 (1995-01-01), None
patent: 0273665 A2 (1988-07-01), None
patent: 0475639 A2 (1992-03-01), None
Berinato, Scott. “New Hard-Disk Specs from WD”, PC Week, Dec. 2, 1996 [online], [retrieved Sep. 7, 2000]. Retrieved from www5.zdnet.com/zdnn/content/pcwk/1348/pcwk0119.html.
M. Yoshida et al., “High Performance Cache Disk Subsystem”, Jun. 1994, pp. 129-134, Hitachi Review, Tokyo Japan.
Western Digital Corp., Western Digital Develops SDX Technology For Hard Drives That Improve Price/Performance of Removable Media Storage Peripherals, Sep. 4, 1997 pp. 1-5.
Western Digital Corp., “SDX (Storage Data Acceleration)”, Technology for Enhanced Peripheral Performance, 1997.
G. Hoffman et al., “IEEE 1394: A Ubiquitous Bus”, presented at COMPCON '95, Mar. 1995, San Francisco, CA.
Leb{acute over (e)}gue Xavier
Schweer Rainer
Bragdon Reginald G.
Burke Alexander J.
Deutsche Thomson-Brandt GmbH
Kurdyla Ronald H.
Tripoli Joseph S.
LandOfFree
Cache enabling architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache enabling architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache enabling architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2491626