Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-09-18
2007-09-18
Chase, Shelly (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
10418546
ABSTRACT:
A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted.
REFERENCES:
patent: 4712216 (1987-12-01), Glaise
patent: 6408417 (2002-06-01), Moudgal et al.
patent: 6742159 (2004-05-01), Sakurai
patent: 6802039 (2004-10-01), Quach et al.
Cargnoni Robert Alan
Guthrie Guy Lynn
Livingston Kirk Samuel
Starke William John
Chase Shelly
International Business Machines - Corporation
Musgrove Jack V.
Salys Casimer K.
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