Cache directory addressing scheme for variable cache sizes

Details Cache directory addressing scheme for variable cache sizes Cache directory addressing scheme for variable cache sizes

1998-03-23

2000-12-05

Cabeca, John W.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711128, 711171, 711172, G06F 1200

Patent

active

061579807

ABSTRACT:
To avoid multiplexing within the critical address path, the same field from an address is employed to index rows within a cache directory and memory regardless of the size of the cache memory. Depending on the size of the cache memory being employed, different address bits (such as Add[12] or Add[25] are employed as a "late select" for the last stage of multiplexing within the cache directory and cache memory. Since smaller address tag fields are employed for the larger cache memory size, the extra address tag bit is forced to a logic 1 within the cache directory and compared to a logic 1 by address tag comparators at the output of the cache directory.

REFERENCES:
patent: 5450565 (1995-09-01), Nadir et al.
patent: 5509135 (1996-04-01), Steely, Jr.
patent: 5561781 (1996-10-01), Braceras et al.
patent: 5564034 (1996-10-01), Miyake
patent: 5778428 (1998-07-01), Batson et al.

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