Cache directed sequential prefetch

Details Cache directed sequential prefetch Cache directed sequential prefetch

2011-06-07

2011-06-07

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S130000, C711S141000, C711S144000, C711S145000

Reexamination Certificate

active

07958317

ABSTRACT:
A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the cache line. A next cache line is prefetched when a previously prefetched cache line is accessed, so that the cache always attempts to prefetch one cache line ahead of accesses, in the direction of a detected stream. Stream detection is performed in response to load misses tracked in the load miss queue (LMQ). The LMQ stores an offset indicating a first miss at the offset within a cache line. A next miss to the line sets a direction bit based on the difference between the first and second offsets and causes prefetch of the next line for the stream.

REFERENCES:
patent: 6535962 (2003-03-01), Mayfield et al.
patent: 7350029 (2008-03-01), Fluhr et al.
patent: 7380066 (2008-05-01), Griswell, Jr. et al.
patent: 2009/0070556 (2009-03-01), Griswell et al.
patent: 2009/0198950 (2009-08-01), Arimilli et al.

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