Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-11-08
2005-11-08
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S121000, C711S124000, C711S141000
Reexamination Certificate
active
06963953
ABSTRACT:
It assumes that “SO” represents a state, in which that data in a responsible region storing the data to be accessed most frequently by the corresponding processor is updated in a cache memory to be controlled by a cache device, and other data is stored in other cache memory. In this case, one or more cache devices controlling each of the remaining cache memories changes the state of the data in a region other than the responsible region of the cache memory controlled by itself from “SN” to “I” (invalid). Therefore, in the case where the data designated by the same address is shared by the plurality of cache memories, the data can be invalidated in the cache memories other than the cache memory corresponding to the processor including the designated address in its own responsible region. Therefore, a data sharing rate can be low.
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McDermott Will & Emery LLP
Portka Gary
Renesas Technology Corp.
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