Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-07-12
2005-07-12
Anderson, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S144000, C711S213000
Reexamination Certificate
active
06918009
ABSTRACT:
In the case that at the time of generation of a pre-fetch request following a read request from one of the processors the data stored in other cache devices cannot be read unless its state tag is changed, a cache controller carries out weak read operation for causing failure in the pre-fetch request as a fetch protocol. Alternatively, the cache controller reads pre-fetch data without changing state tags of other cache devices, sets a weak read state (W), and stores the data. The data in the weak read state (W) is invalided by synchronization operation of memory consistency by software. Furthermore, the pre-fetch data is stored in a passive preservation mode in the present cache device. Even if the pre-fetch data corresponds to a read request from some other cache device, the preservation of the data is not informed to the other cache device.
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Kumon Kouichi
Sato Mitsuru
Anderson Matthew
Fujitsu Limited
Patel Hetul
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