Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-05-16
1999-09-28
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711203, G06F 1210, G06F 1208
Patent
active
059604638
ABSTRACT:
Table walk logic and a second level access logic are tightly coupled to each other in a second level control unit that can operate in one of two modes, a translate mode that uses the table walk logic and an access mode that uses the second level access logic. In the translate mode, the second level control unit uses the table walk logic for automatic translation of a virtual address to a corresponding physical address. In the access mode, the second level control unit allows a word to be loaded from or stored into a given physical address. The second level control unit prioritizes operations in the two modes e.g. performs an operation in the access mode prior to performance of an operation in the translate mode. The table walk logic and the second level access logic can be integrated together into a single state machine, so that operations in the two modes are mutually exclusive and indivisible with respect to each other. Tight coupling of the two logics fundamentally enhances address translation circuitry, e.g. saves space and increases speed, as compared to prior art devices. Such tight coupling also eliminates an access into the first level cache for address translation, eliminates pollution of the first level cache by table entries and also reduces contention for the first level cache.
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Favor John Gregory
Sharma Puneet
Advanced Micro Devices , Inc.
Chan Eddie P.
Encarnacion Yamir
Suryadevara Omkar K.
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