Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-09-15
2000-06-13
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711158, 711150, 711 3, G06F 1200, G06F 1300
Patent
active
060761504
ABSTRACT:
A cache controller with an improved cache memory refill operation is presented. After a request from a CPU for a word of information and the word is not found in the cache memory, the cache controller starts a refill operation by which a line of information including the requested word is loaded into the cache memory from a main memory. The cache controller keeps track of the CPU requests. When a requested word appears during the refill operation, the CPU is notified to load the requested word as the word is loaded into the cache memory. Furthermore, the cache controller efficiently takes advantage of free cycles in the refill operation. If the CPU has requested a word in the cache memory, the cache controller reads the word from the cache memory so the CPU can load the word during a free cycle.
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Chan Eddie P.
Kim Hong
Kivlin B. Noel
LSI Logic Corporation
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