Cache controller unit architecture and applied method

Details Cache controller unit architecture and applied method Cache controller unit architecture and applied method

2005-12-13

2005-12-13

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000

Reexamination Certificate

active

06976130

ABSTRACT:
A cache controller unit (CCU) architecture with dirty line write-back auto-adjustment, suitable for high performance microprocessor systems with write-back cache memory. The CCU architecture includes a cache data control unit to access data between a cache memory and a CPU, a tag compare unit to compare an address sent by the CPU and a tag address sent by a tag memory and thus produce a cache hit signal, and a CCU state machine to control the data access direction of the cache data control and produce corresponding operations according to the tag compare result.

REFERENCES:
patent: 5247643 (1993-09-01), Shottan
patent: 5404483 (1995-04-01), Stamm et al.
patent: 6065099 (2000-05-01), Clark et al.

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