Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-06-07
2005-06-07
Tran, Denise (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711S156000, C711S159000
Reexamination Certificate
active
06904500
ABSTRACT:
A cache controller operable to control a cache comprising cache lines, each being operable to store data words and validity information indicating that all data words within that cache line are valid. The cache controller comprises a linefill mechanism operable to write data words to a cache line, to provide an indication when each of the data words has been written to the cache and to set the validity information when all data words in the cache line have been written; and a data word accessing mechanism, responsive to a request to access a data word during a linefill operation prior to the validity information being set, to determine from the indication provided by the linefill mechanism whether the data word to be accessed has already been written during the linefill operation and, if so, to provide a signal indicating that the data word is accessible.
REFERENCES:
patent: 5781916 (1998-07-01), Hardage et al.
patent: 5781926 (1998-07-01), Gaskins et al.
patent: 5835929 (1998-11-01), Gaskins et al.
patent: 2003/0110356 (2003-06-01), Williams, III
Grisenthwaite Richard Roy
Gwilt David John
ARM Limited
Tran Denise
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