Cache control system equipped with a loop lock indicator for ind

Details Cache control system equipped with a loop lock indicator for ind Cache control system equipped with a loop lock indicator for ind

1993-11-23

1996-04-23

Chan, Eddie P.

Boots, shoes, and leggings

395460, 364DIG1, 36424341, G06F 1202

Patent

active

055111785

ABSTRACT:
In a cache memory 20, there exist a plurality of cache lines 201, each of which is equipped with a loop lock L for indicating that an instruction is present in a feedback loop section. The states of the loop locks L are dynamically changed according to the executed state of a program. At the time of excluding the cache lines for a prefetch, the instruction string in the loop is held in the cache memory 20 till the program control transfers to the outside of the loop.

REFERENCES:
patent: 4513367 (1985-04-01), Chan et al.
patent: 4977498 (1990-12-01), Rastegar et al.
patent: 5353425 (1994-10-01), Malamy et al.
"ADJ-602-065 of Section 6 Cache," Temporary Version of Hitachi 32--bit RISC Processor PA/10 HD69010 Hardware Manual, pp. 83-85. (English translation provided).

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