Cache control device and manufacturing method thereof

Details Cache control device and manufacturing method thereof Cache control device and manufacturing method thereof

2005-04-19

2005-04-19

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06883069

ABSTRACT:
A cache control device comprises a command control section43for receiving a cache deterioration report and generating a cache flush mode initiation signal which performs degeneration of the cache44, a software interrupt section52for interrupting the supply of commands from software in response to the cache flush mode initiation signal, a command generating section53afor generating fetch requests in which cache data flushing occurs to the cache in response to the cache flush mode initiation signal, an address generating section54for generating addresses for flushing the cache data in response to the cache flush mode initiation signal, and a request counter58for specifying ways at which flushing of the cache will be performed, whereby degeneration is possible where different CPUs are mounted in the system, or where a CMP micro architecture is employed, without the necessity of changing the system hardware or OS, or making additions to the computer architecture.

REFERENCES:
patent: 5784394 (1998-07-01), Alvarez et al.
patent: 20030188219 (2003-10-01), DeRuiter et al.
patent: 6-4336 (1994-01-01), None
patent: 8-221215 (1996-08-01), None

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