Cache control circuitry and method therefor

Details Cache control circuitry and method therefor Cache control circuitry and method therefor

1996-03-25

1998-07-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711143, 711144, G06F 1208

Patent

active

057819165

ABSTRACT:
After a portion of a cache line has been zone written from a processor core (102) to a cache array (105), a read access received from the processor core (102) for one or more bytes within the cache line corresponding to the zone written data can be satisfied before a cache fill operation initiated by the zone written operation is completed. If the read access is for one or more bytes of the cache line which was not previously zone written, then the requested data is passed directly from the filling bus (113) to the processor core (102) as soon as it becomes valid on the filling bus (113). If the read access is for one or more bytes of the zone written data, then those one or more bytes are read from the cache array (105) to the processor core (102) regardless of the progress of the cache fill. All read accesses to filling cache lines are serviced in the minimum amount of time by satisfying the access immediately upon availability of only the exact portion requested.

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Knebel, Patrick et al., "HP's PA7A7100LC: A Lov-Cost Superscaler PA-RISC Processor," IEEE, 1993, p. 441-447.

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