Cache control circuit having a pseudo random address generator

Details Cache control circuit having a pseudo random address generator Cache control circuit having a pseudo random address generator

1997-04-03

1999-02-23

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711123, 711128, 711129, 711145, 36471703, G06F 1208

Patent

active

058754652

ABSTRACT:
A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.

REFERENCES:
patent: 5434992 (1995-07-01), Mattson

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