Cache control apparatus and method with pipelined, burst read

Details Cache control apparatus and method with pipelined, burst read Cache control apparatus and method with pipelined, burst read

1994-03-17

1995-05-16

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

36518905, G11C 1300

Patent

active

054167396

ABSTRACT:
A cache memory controller capable of servicing pipelined multi-word read memory requests issued by a processor wherein requested data if found to be within a cache memory is bursted to the processor and wherein the servicing of a second pipelined multi-word read memory request issued by the processor overlaps in time with the servicing of a first pipelined multi-word read memory request.

REFERENCES:
patent: 5177706 (1993-01-01), Shinohara et al.

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