Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-03-21
1998-07-28
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711113, 711124, 711202, G06F 1200
Patent
active
057874670
ABSTRACT:
A cache control apparatus for controlling address mapping of a cache memory which can dynamically change the mapping algorithm of the address mapping. The cache control apparatus has a plurality of mapping controllers individually provided for different mapping algorithms each for producing a set address and an address tag in response to an output of said address register, a mapping algorithm controller for selecting one of the mapping controllers and outputting a selector control signal, a first selector for selecting one of the set addresses outputted from the mapping controllers, a second selector for selecting one of the address tags outputted from the mapping controllers, a comparison circuit for comparing the address tags outputted from the second selector and a tag memory, a hit discrimination circuit for discriminating a cache hit based on a result of the comparison by the comparison circuit, and hit ratio calculation means for calculating a cache hit ratio. The mapping algorithm controller selecting one of the mapping controllers based on the cache hit ratio calculated by the hit ratio calculation means.
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NEC Corporation
Swann Tod R.
Tzeng Fred Fei
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