Cache consistency in a multiprocessor system with shared memory

Details Cache consistency in a multiprocessor system with shared memory Cache consistency in a multiprocessor system with shared memory

2006-06-27

2010-06-22

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000

Reexamination Certificate

active

07743217

ABSTRACT:
A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

REFERENCES:
patent: 5522057 (1996-05-01), Lichy
patent: 6145059 (2000-11-01), Arimilli et al.
patent: 2003/0131201 (2003-07-01), Khare et al.
patent: 2005/0027945 (2005-02-01), Desai
Preliminary Search Report, FR 05 06657, dated Mar. 1, 2006.

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