Cache coherency scheme for XBAR storage structure with delayed i

Details Cache coherency scheme for XBAR storage structure with delayed i Cache coherency scheme for XBAR storage structure with delayed i

1994-12-27

1997-02-11

Swann, Tod R.

Boots, shoes, and leggings

395312, 395471, 395874, 364DIG1, G06F 1300

Patent

active

056030053

ABSTRACT:
A method and apparatus for identifying obsolete data within cache memory in a multiprocessor architecture. This is accomplished while still providing the advantages of having cache resources dedicated to individual instruction processors as well as shared intermediate level cache modules. The technique provides the band pass and attendant performance advantages of an essentially point-to-point architecture without all of the added hardware of a centralized master system storage controller. Further, unlike a strictly point-to-point architecture, the present invention is readily expandable to service a large number of multiprocessors without burdening each of the multiprocessors with the corresponding increase in interface and connection costs of a strictly point-to-point architecture. This simplifies the design of the multiprocessor elements and also allows a system to be expanded to include more or less multiprocessors by simply including a modified XBAR interface. In a strictly point-to-point architecture, the multiprocessors may have to be modified to expanding a system because the interfacing circuitry associated therewith is contained therein. The present invention further has a means for increasing the performance of the XBAR interface by providing an anticipatory acknowledge signal back to a requesting multiprocessor.

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