Cache coherency in a shared-memory multiprocessor system

Details Cache coherency in a shared-memory multiprocessor system Cache coherency in a shared-memory multiprocessor system

2011-06-28

2011-06-28

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S147000, C711S150000, C711S151000, C711S158000

Reexamination Certificate

active

07971003

ABSTRACT:
A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

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