Cache coherency during resynchronization of self-correcting...

Details Cache coherency during resynchronization of self-correcting... Cache coherency during resynchronization of self-correcting...

2006-02-16

2008-08-19

Wilson, Yolanda L (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S012000, C714S013000

Reexamination Certificate

active

07415630

ABSTRACT:
A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled.

REFERENCES:
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patent: 5864657 (1999-01-01), Stiffler
patent: 6622216 (2003-09-01), Lin
patent: 2004/0068595 (2004-04-01), Dieffenderfer et al.
Wikipedia—en.wikipedia.org/wiki/PCI—bus.

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