Cache coherency control method, chipset, and multi-processor...

Details Cache coherency control method, chipset, and multi-processor... Cache coherency control method, chipset, and multi-processor...

2006-08-31

2009-11-03

Chace, Christian P (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S147000, C711S148000, C711S153000

Reexamination Certificate

active

07613885

ABSTRACT:
In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy tag information. When the local node's cache copy tag information is available, the memory access latency can be shortened by omitting a process to count snoop results. When memory position information is used to update the cache copy tag during cache replacement, it is possible to increase a ratio to hit a copy tag during reaccess from the local node.

REFERENCES:
patent: 6901485 (2005-05-01), Arimilli et al.
patent: 2003/0177317 (2003-09-01), Anderson et al.
patent: 10-222423 (1998-08-01), None
“Implementation of Mission Critical Linux on ES 700 ” Unisys Technology Review, Feb. 2005.pp. 56-69.
Origin ccNUMA Servers True Scalability with a Difference, Silicon Graphics Computer Systems, 1999.
“The SGI Origin: AccNUMA Highly Scalable Server” by Laudon, et al., 1998 (with English translation).

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