Cache coherency arrangement to enhance inbound bandwidth

Details Cache coherency arrangement to enhance inbound bandwidth Cache coherency arrangement to enhance inbound bandwidth

2005-01-11

2005-01-11

Lane, Jack A. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S146000, C711S137000, C710S039000, C710S040000

Reexamination Certificate

active

06842827

ABSTRACT:
A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.

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