Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-01-07
2001-03-27
Rinehart, Mark H. (Department: 2756)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S173000, C711S202000, C711S205000, C711S206000, C711S221000
Reexamination Certificate
active
06209064
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computer communication protocols, and more specifically to an integrated protocol that supports both shared memory cache coherence and protected shared nothing message passing.
2. Description of Background Art
One class of multi-processor data computer system consists of a plurality of processor nodes communicating over a high-speed interconnection. Each processor node typically includes a processor and local Random Access Memory (RAM). A computational problem may be divided among processor nodes to use the particular resources available at different processor nodes or to reduce the real time needed to produce a result and thereby expedite the computation. Hence, a process running on one processor node may depend on computations being performed at other processor nodes in the computer system. The various processes communicate over the interconnection to exchange information and synchronize the processes.
There are two major multiprocessor programming paradigms that differ by how the processors communicate with one another. The shared memory paradigm allows all processors to access all memory in the entire machine. Processors communicate with each other by one processor writing a value to a given memory location and another processor reading that value from the same memory location. In contrast, in the shared nothing (or message-passing) paradigm, each processor can only access its own memory, and communicates with other processors by explicitly building messages and sending them to the other processor. Both programming paradigms have their relative merits and both are used. An advantage of the shared-memory paradigm is that it offers more efficient communication, whereas an advantage of the shared-nothing paradigm is that it offers greater protection of one process from all other processes.
Prior art systems usually allow only one or the other programming paradigm. If both are allowed, then they are usually supported over two different types of interconnects, usually a high-performance interconnect for shared memory and the associated cache coherence protocol, and a lower-performance interconnect for message-passing.
SUMMARY OF THE INVENTION
The objects of the present invention include the integration of a shared memory cache coherence protocol and a shared nothing message passing protocol onto the same high-performance interconnect and to raise protection boundaries between processors not sharing memory while allowing complete access to processors sharing memory.
The invention resides in a system and method for a message passing protocol to extend cache coherence management of scalable shared-memory multiprocessing computer systems. The scalable shared-memory multiprocessing computer system has a plurality of processors connected to an interconnection over which the processors communicate between themselves. The interconnection processors use a communication protocol which is adaptable for shared-memory computer systems, shared nothing computer systems, and hybrid computer systems in which some processors share memory while others do not, to send and receive messages on the interconnection. For hybrid computer systems it is important to raise protection boundaries between processors not sharing memory while allowing complete access to processors sharing memory. A processor node is able to tell whether an incoming message is from within the same coherence group (in which case it is completely unprotected) or is from outside the coherence group (in which case the shared-nothing protections apply). This allows processor nodes sharing memory and processor nodes sharing nothing to co-exist on the same interconnection. This is achieved by using node identification numbers (NIDs), coherence node numbers (CNNs), and a mapping between them. Each processing node in the system is given a NID. Nodes in a set which will share memory are each assigned a CNN and agree on a consistent mapping of CNNs to NIDs. With this mapping a processor node is able to tell whether an incoming message is from within the same coherence group (in which case it is completely unprotected) or is from outside the coherence group (in which case the shared-nothing protections apply). This allows processor nodes sharing memory and processor nodes sharing nothing to co-exist on a common interconnection.
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Carr & Ferrell LLP
Fujitsu Limited
Rinehart Mark H.
Willett Stephan
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