Cache coherence for lazy entry consistency in lockup-free caches

Details Cache coherence for lazy entry consistency in lockup-free caches Cache coherence for lazy entry consistency in lockup-free caches

1997-07-01

2000-07-25

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711119, 711147, G06F 1200

Patent

active

060947098

ABSTRACT:
A method of reducing false sharing in a shared memory system by enabling two caches to modify the same line at the same time. More specifically, with this invention a lock associated with a segment of shared memory is acquired, where the segment will then be used exclusively by processor of the shared memory system that has acquired the lock. For each line of the segment, an invalidation request is sent to a number of caches of the system. When a cache receives the invalidation request, it invalidates each line of the segment that is in the cache. When each line of the segment is invalidated, an invalidation acknowledgement is sent to the global directory. For each line of the segment that has been updated or modified, the update data is written back to main memory. Then, an acquire signal is sent to the requesting processor which then has exclusive use of the segment.

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