Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-07-19
2005-07-19
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S145000, C711S133000, C711S159000, C709S218000
Reexamination Certificate
active
06920532
ABSTRACT:
Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster which are cached in remote clusters. The cache coherence controller is operable to initiate eviction of an entry in its directory corresponding to a modified copy of a memory line by sending a request to merge an empty data field with the modified copy of the memory line to a corresponding memory controller.
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Glasco David Brian
Kota Rajesh
Valluru Sridhar K.
Beyer Weaver & Thomas LLP
Kim Hong
Newisys Inc.
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