Cache circuit with programmable sizing and method of operation

Details Cache circuit with programmable sizing and method of operation Cache circuit with programmable sizing and method of operation

1997-05-30

1999-08-17

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

G06F 1208

Patent

active

059408588

ABSTRACT:
For use in an x86-compatible processor having a cache, a circuit and method for setting a size of the cache and a computer system employing the circuit or the method. In one embodiment, the circuit includes: (1) multiple access circuitry dividing the cache into separate physically-addressable sectors and (2) sector disabling circuitry, coupled to the cache, that selectively allows at least one of the sectors to be disabled to decrease the size of the cache.

REFERENCES:
patent: 4357656 (1982-11-01), Saltz et al.
patent: 5253203 (1993-10-01), Partovi et al.
patent: 5819114 (1998-10-01), Behnke

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