Cache buffer control apparatus and method using counters to...

Details Cache buffer control apparatus and method using counters to... Cache buffer control apparatus and method using counters to...

2005-09-13

2005-09-13

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S156000, C711S159000, C710S057000

Reexamination Certificate

active

06944717

ABSTRACT:
Methods for controlling and storing data in a cache buffer in a storage apparatus having a nonvolatile memory medium are disclosed. Memory cells are logically divided into a plurality of pages. An open status is registered in a counter for each page that has at least some (and usually all) memory cells available to store new data. A full status is registered in the counter for each page that does not have memory cells that are available to store new data. New data is stored in pages having the open status in the counter. The pages can be weighted according to the read command rate and prioritized for reading and writing purposes.

REFERENCES:
patent: 5909695 (1999-06-01), Wong et al.
patent: 6016529 (2000-01-01), Woodman
patent: 6065099 (2000-05-01), Clark et al.
patent: 6189080 (2001-02-01), Ofer
patent: 6209062 (2001-03-01), Boland et al.
patent: 6598125 (2003-07-01), Romm

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