Cache based physical layer self test

Details Cache based physical layer self test Cache based physical layer self test

2007-04-10

2007-04-10

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S715000, C714S735000, C714S043000, C714S044000

Reexamination Certificate

active

10882966

ABSTRACT:
A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

REFERENCES:
patent: 6617842 (2003-09-01), Nishikawa et al.
patent: 6651205 (2003-11-01), Takahashi
patent: 6826100 (2004-11-01), Ellis et al.
patent: 2004/0097093 (2004-05-01), Fukuyama et al.

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