Cache-based computer system employing memory control circuit and

Details Cache-based computer system employing memory control circuit and Cache-based computer system employing memory control circuit and

1997-07-18

1999-05-11

Lane, Jack A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711133, 711137, G06F13/00

Patent

active

059039116

ABSTRACT:
A cache-based computer system is provided that attains the advantages of data prefetching while minimizing negative affects upon system bandwidth and overall system performance. When a microprocessor initiates a write cycle and a cache miss occurs, a master prefetch control circuit within a cache controller initiates a specialized bus transfer cycle referred to as a "write allocation and prefetch cycle". A slave prefetch control circuit responds to the initiation of the write allocation and prefetch cycle by latching the data from the microprocessor into a temporary storage element of a memory controller. The slave prefetch control circuit also initiates a burst read cycle simultaneously to access a corresponding block or line of prefetched data stored in system memory. The prefetched data is sequentially provided to the system bus and into the cache memory. Once the entire data block is read from system memory and transferred into the cache memory, the write data stored within the temporary storage element is written into the system memory.

REFERENCES:
patent: 4298929 (1981-11-01), Capozzi
patent: 4366539 (1982-12-01), Johnson et al.
patent: 4649511 (1987-03-01), Gdula
patent: 4816997 (1989-03-01), Scales, III et al.
patent: 5091845 (1992-02-01), Rubinfeld
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5155824 (1992-10-01), Edenfield et al.
patent: 5179679 (1993-01-01), Shoemaker
patent: 5197144 (1993-03-01), Edenfield et al.
patent: 5224214 (1993-06-01), Rosich
patent: 5251310 (1993-10-01), Smelser
M. Morris Mano, "Digital Design", Chapter 6, Prentice-Hall, Inc., 1984, pp. 220-229, 233-238 and pp. 305-307.
Thomas C. Bartee, "Digital Computer Fundamentals", sixth edition, McGraw-Hill Book Company, 1985, pp. 170-175.

Affiliated with

Also associated with

Rating

Cache-based computer system employing memory control circuit and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache-based computer system employing memory control circuit and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache-based computer system employing memory control circuit and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-255793