Cache bank conflict avoidance and cache collision avoidance

Details Cache bank conflict avoidance and cache collision avoidance Cache bank conflict avoidance and cache collision avoidance

1997-12-16

2000-02-22

Cabeca, John W.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711 3, 711157, 711140, 711158, 711165, 711210, G06F 1200

Patent

active

060292253

ABSTRACT:
The inventive mechanism determines whether memory source and destination addresses map to the same or nearly the same cache address. If they map to different addresses, then loads and stores are ordered so that loads to one cache bank are performed on the same clock cycles as the stores to another cache bank. After a group of loads and stores are completed, then load and store operations for each bank are switched. If the source and destination addresses map to nearly the same cache address and if the source address is prior to the destination address, then a group of cache lines is loaded into registers and stored to memory without any interleaving of other loads and stores. If the source and destination addresses map to the same cache location, then an initial load of data into registers is performed. After that, additional loads are interleaved with non-cache conflicting stores to move new values into memory. Thus, loads and stores to matching cache addresses are separated by time.

REFERENCES:
patent: 5084791 (1992-01-01), Thanos et al.
patent: 5134563 (1992-07-01), Tayler et al.
patent: 5644742 (1997-07-01), Shen et al.
patent: 5845106 (1998-12-01), Stapleton

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