Cache-aware scheduling for a chip multithreading processor

Details Cache-aware scheduling for a chip multithreading processor Cache-aware scheduling for a chip multithreading processor

2005-11-03

2010-10-19

An, Meng-Ai (Department: 2195)

Electrical computers and digital processing systems: virtual mac

Task management or control

Process scheduling

C718S107000, C711S001000, C711S113000, C711S118000, C711S147000, C711S170000

Reexamination Certificate

active

07818747

ABSTRACT:
A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

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