Cache-aware scheduling for a chip multithreading processor

Details Cache-aware scheduling for a chip multithreading processor Cache-aware scheduling for a chip multithreading processor

2005-11-03

2009-02-03

Sough, Hyung S (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S118000, C711S130000, C711S140000, C711S169000, C718S102000

Reexamination Certificate

active

07487317

ABSTRACT:
A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

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