Cache array select logic allowing cache array size to differ fro

Details Cache array select logic allowing cache array size to differ fro Cache array select logic allowing cache array size to differ fro

1996-05-20

1998-09-15

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711 3, 711202, 711206, 711118, 711119, 711125, G06F 1202

Patent

active

058095624

ABSTRACT:
An apparatus and method for organizing a data array within a cache system to store a plurality of physical pages of data. A single data array is associated with a plurality of tag arrays, each tag array tracking a page size portion of the data array. Indexing into each of the tag arrays is accomplished using the page index from either of the virtual address or the physical address. In addition, selection of indexed tags from the tag arrays is performed by array selection logic which utilizes portions of either of the virtual page number or the physical page number.

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patent: 5410669 (1995-04-01), Biggs et al.
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