Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-04-14
1999-09-28
Palys, Joseph E.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 42, 714 43, 714 44, 714 52, 714 54, 711133, 711144, G06F 1100
Patent
active
059580682
ABSTRACT:
A method of bypassing defects in a cache used by a processor of a computer system. A repair mask has an array of bit fields corresponding to cache lines in the cache, and when a particular cache line in the cache is identified as being defective, a corresponding bit field in the repair mask array is set to indicate that the particular cache line is defective, and further access to the defective cache line is prevented, based on the corresponding bit field in the repair mask array. The repair mask can be used to prevent the defective cache line from ever resulting in a cache hit, and to prevent the defective cache line from ever being chosen as a victim for cache replacement. Using a set associative cache, the defective cache line is thereby effectively removed from its respective congruence class. This approach allows the cache to use all non-defective cache lines without any cache lines being reserved for redundancy.
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Arimilli Ravi Kumar
Dodson John Steven
Lewis Jerry Don
Skergan Timothy M.
Dillon Andrew J.
Henkler Richard A.
International Business Machines - Corporation
Mai Rijue
Musgrove Jack V.
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