Cache arrangement including coalescing buffer queue for non-cach

Details Cache arrangement including coalescing buffer queue for non-cach Cache arrangement including coalescing buffer queue for non-cach

1995-08-17

1997-09-02

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395874, 711154, G06F 1208

Patent

active

056641486

ABSTRACT:
An apparatus including a cache subsystem arrangement for efficient management of input/output operations and of memory shared by processors in a multiprocessor system. The apparatus includes a central processing unit, an input/output device such as a network device or a display device for example, and the cache arrangement, which includes a coalescing buffer coupled with the data processing unit for receiving non-cacheable data from the processing unit. The non-cacheable data is combined in the coalescing buffer into non-cacheable data blocks. A system bus is coupled with the buffer and the input/output device for storing the non-cacheable data blocks to the input/output device. By combining the non-cacheable data before storage to the input/output device, the coalescing buffer provides higher performance in the multiprocessor system, since fewer bus transactions are issued for serial store operations and more stores can complete in a given amount of time than if they were issued singly on the bus. This is particularly advantageous in the multiprocessing system since multiple processors must compete for limited bus transaction bandwidth.

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Publication No.: 06314252 A; Published: Nov. 8, 1994; Applicant: Hitachi, Ltd., p. 1.

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