Cache architecture for a processing unit providing reduced...

Details Cache architecture for a processing unit providing reduced... Cache architecture for a processing unit providing reduced...

2011-06-21

2011-06-21

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S126000, C711SE12062

Reexamination Certificate

active

07966452

ABSTRACT:
A cache memory processing system is disclosed that is coupled to a main memory and a processing unit. The cache memory processing system includes an input, a low order bit data path, a high order bit data path and an output. The input is for receiving input data that includes at least one low order input bit and at least one high order input bit. The low order bit data path is for processing the at least one low order input bit and providing at least one low order output bit. The high order bit data path for processing the at least one high order input bit and providing at least one high order output bit. The high order bit data path includes at least one exclusive or gate. The output is for providing the at least one low order output bit and the at least one high order output bit.

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Yang, Jun et al. “Energy Efficient Frequent Value Data Cache Design”, Microarchitecture, 2002. (MICRO 35). Proceedings. 35th Annual IEEE/ACM International Symposium on Nov. 18-22, 2002. Picataway, NJ, USA, pp. 197-207.

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