Cache apparatus for enabling overlap of instruction fetch operat

Details Cache apparatus for enabling overlap of instruction fetch operat Cache apparatus for enabling overlap of instruction fetch operat

1978-12-11

1982-01-26

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900

Patent

active

043131581

ABSTRACT:
A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes control apparatus, an instruction buffer for storing instructions received from main store and a transit block buffer comprising a plurality of locations for storing read commands. The control apparatus includes a plurality of groups of bit storage elements corresponding to the number of transit buffer locations. Each group includes at least a pair of instruction fetch indicator elements which are operatively connected to control the writing of first and second blocks of instructions into the instruction buffer. Each time a read command specifying the fetching of instructions of either a first or second block is received from the processing unit, the flag storage element associated with the transit block buffer location into which the read command is loaded is set to a binary ONE state while the corresponding ones of the flag storage elements associated with the other locations storing outstanding read commands specifying instruction fetches are reset to binary ZEROS. This permits only those instructions received from main store in response to that read command to be loaded into a specified section of the instruction buffer for enabling overlaps in processing several commands specifying instruction fetch operations.

REFERENCES:
patent: 3588829 (1971-06-01), Boland

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