Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-06-15
2003-09-30
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S030000, C712S225000, C711S100000
Reexamination Certificate
active
06629168
ABSTRACT:
TECHNICAL FIELD
The invention relates to computer and memory systems. More particularly, the invention relates to efficiency enhancement of memory usage.
BACKGROUND ART
Various components of a computing system utilize memory devices to store and/or retrieve information. Usage of memory devices is not limited to a main computer unit, e.g., the mother board, but is ubiquitous in virtually every component of a computing system, e.g., input/output (I/O) devices (e.g., keyboards, pointing devices, display monitors and the like), peripheral devices (e.g., hard drives, tape drives, printers and the like) and bus and/or network interface devices (e.g., bus bridges, local area network (LAN) interface cards). There are various types of memory devices currently available in the market, e.g., a dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable read-only memory (EEPROM), a hard disk or the like, to which data can be written, and from which data may be read.
Often, a memory device is used as a data buffer to temporarily store received data before sending the same to another component of the computing system, and to thus lessen the effects of data transfer speed differences between various components of the computing system. For example, a host interface device allows a peripheral and/or an I/O device, e.g., a hard drive, a tape drive or the like, to communicate with a host computing system, e.g., a personal computer (PC) or the like, and includes a buffer memory to temporarily hold data being transferred between the host computing system and the peripheral and/or the I/O device. One of the widely accepted standards for host interface is the Small Computer System Interface (SCSI) standard, which is specified by the American National Standards Institute (ANSI X3. 131-1986, which is incorporated herein by reference in its entirety) of New York, N.Y., U.S.A.
Unfortunately, while a memory device allows adequate data transfer between computing entities having different data transfer rates, there are a number of drawbacks in a conventional buffer memory. In particular, while memory devices are typically organized into a plurality of words of fixed lengths (which are accessed one at a time), an access request to and from the memory devices, i.e., a write or a read, may result in a variable number of bytes of data transfer. For example, a host interface device based on the SCSI protocol transfers data in blocks that may be of fixed or variable length, e.g., varying from 1 byte to 2
24
-1 bytes. The buffer memory embedded in the host interface device, however, may be organized into 36 bit words (32 bits of data, i.e., 4 bytes, and 4 bits for control, e.g., error correction or the like), and may be accessed a word at a time.
When an access request to the buffer memory involves a transfer of data block of size which is not a multiple of four bytes, at least one word of the buffer memory is left only partially filled. For example, a write of five bytes to the buffer memory would write to two words, the second word of which containing only one byte, and having three bytes remaining unused. Because, in a conventional buffer memory system, the next write to the buffer memory would write to a new word, i.e., a subsequent memory location, the three unused byte locations of the buffer memory are left unused until the partially filled word location is written to again. As can be appreciated, a conventional buffer memory system may have many gaps of unused memory locations at any given time due to transfers of partial words, and is thus wasteful of valuable buffer memory space.
Thus, there is a need for a more efficient method of and system for providing a buffer memory, which utilizes every available memory space of the buffer memory.
SUMMARY OF INVENTION
In accordance with the principles of the present invention, a method of transferring data to and from a buffer memory organized into a plurality of fixed length words comprises receiving a request to transfer a first data, determining if transfer of the first data results in a transfer of a partial word, storing, if transfer of the first data results in a transfer of a partial word, the partial word in a temporary holding area, receiving a subsequent request to transfer a second data, and transferring, if at least a portion of the second data and the partial word together have a sufficient size to produce a complete word, the complete word comprising at least a portion of the second data and the partial word combined together.
In accordance with another aspect of the present invention, an apparatus for transferring data to and from a buffer memory organized into a plurality of fixed length words comprises a data bus configured to receive a request to transfer a first data and a subsequent request to transfer a second data, a temporary holding area for storing, if transfer of the first data results in the transfer of a partial word, the partial word, a buffer management unit in operable communications with the data bus, the buffer memory and the temporary holding area, the buffer management unit configured to transfer, if transfer of the first data results in a transfer of the partial word, and if at least a portion of the second data and the partial word together have a sufficient size to produce a complete word, the complete word comprising at least a portion of the second data and the partial word combined together.
In accordance with yet another aspect of the present invention, a buffer memory system comprises a buffer memory organized into a plurality of fixed length words, a byte swap register, and a buffer management unit in communication with the buffer memory and the byte swap register, the buffer management unit being configured to store a partial word, resulting from a data transfer request, in the byte swap register, and the buffer management unit being configured to transfer a completed word produced by combining the partial word stored in the byte swap register and at least a portion of data in a subsequent data transfer request.
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patent: 4499539 (1985-02-01), Vosacek
patent: 4680702 (1987-07-01), McCarthy
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patent: 5369651 (1994-11-01), Marisetty
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patent: WO 91/03785 (1991-03-01), None
U.K. Search Report.
Buckley Fintan
Carter Thomas
Hogan Julie
Kroll Kimberly K.
Repman Paula D.
Gaffin Jeffrey
Hewlett-Packard Development Company LP.
Mai Rijue
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