Bypass circuit for bypassing host computer which are connected t

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral monitoring

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710 28, 710 38, 710131, 714 22, 714 30, 714 42, 714 43, C06F 1122

Patent

active

060386185

ABSTRACT:
A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.

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