Bypass capacitance localization

Details Bypass capacitance localization Bypass capacitance localization

2001-12-12

2003-11-25

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

C326S101000, C326S027000, C257S532000, C716S030000

Reexamination Certificate

active

06653858

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is relates to integrated circuit (IC) design and fabrication and, more particularly, to localizing bypassed capacitance with respect to sources of noise within an integrated circuit in order to optimize the effectiveness of the bypass capacitance.
BACKGROUND OF THE INVENTION
In IC design, a design technique known as “data path” is used, in which a bus passes through one macro cell after another, with each macro cell performing particular operations on the bus signals. A macro cell generally is a rectangular, tiled arrangement of leaf cells which performs a function, such as ‘register’, ‘and’ or ‘add’ logical functions on the bus signals. The data path design technique reduces routing complexity of the buses because each bus line enters one side of a cell of the macro cell and exits the opposite side of the cell of the macro cell. For example, assuming the IC comprises two 64-bit buses, a macro cell may comprise 64 cells, each of which comprises an AND gate. Two lines from each of the 64-bit buses pass through each respective cell and the corresponding signals on the two lines are ANDed together. The lines of the buses then exit the opposite side of the cell with signals on them that depend on the operation(s) performed by the cell. Other examples of macro cells include a macro cell having 64 flip flops, 64 exclusive NOR gate (XNOR), etc.
When an IC is designed in this manner with macro cells, the design is normally tiled because the macro cells are designed with respect to the width of the bus, or buses, such that the bus lines enter the top of a cell and exit the bottom of a cell and continue on to, for example, the next macro cell. Therefore, the IC will typically comprise a large number of these macro cells arranged symmetrically. Generally, before the IC is ever designed, a library of data path macro cells is created so that the IC designer will have a full set of macro cells having various types of functionality to work with when designing the IC. The IC designer then builds the data path block, which generally is a stack of the macro cells with appropriate connections made to all of the macro cells and the cells of the macro cells.
It is known to use bypass capacitance in integrated circuits for the purpose of reducing noise in the power supply of the IC. In the past, bypass capacitors have been added at various locations within the IC to control noise in the power supplies. However, the manner in which bypass capacitors have been located within the IC in the past does not optimize the effectiveness of the bypass capacitors at reducing noise. One of the reasons that these techniques are not always effective is that the bypass capacitors are sometimes located a relatively long distance away from the power supplies, which reduces the effectiveness of the bypass capacitors.
Using bypass capacitance in an effective manner to reduce noise on an IC can eliminate unacceptable levels of noise, which can cause incorrect states to occur in the IC and thus prevent the IC from functioning properly. With the clock rates at which ICs are now capable of operating, incredibly high frequency components can be generated in the IC. These high frequency components can cause the power supplies of the IC to become noisy. By connecting a bypass capacitor between the power supply, VDD, and ground, GND, as shown in
FIG. 1
, the high frequency components can be filtered out of the power supply. The bypass capacitor maintains some extra charge local to the power supply that maintains the power supply at the correct voltage level, thereby preventing the power supply from unacceptably fluctuating between one voltage level and another.
FIG. 1
illustrates a circuit diagram of a simple inverter in parallel with a bypass capacitor
1
. When the input signal
2
to the inverter is high, node
3
is high, and the Pfet P
1
is turned off and the Nfet N
1
is turned on, thereby pulling the output node
4
down to ground, GND
5
. When the input signal
2
is low (node
3
is low), the Pfet P
1
is turned on and the Nfet N
1
is turned off, which causes the output to be pulled up to VDD
6
.
Because the input signal
2
can change extremely rapidly in current ICs, the power supply VDD
6
can be “tugged on” at very high rates, which can cause noise to be coupled into the power supply VDD
6
. The bypass capacitor
7
shown in parallel with the inverter and connected on one end to VDD
6
and the other end to ground GND
5
maintains a charge that helps the power supply VDD
6
to remain at a particular desired voltage level despite the speed at which input signal
2
changes. Therefore, the bypass capacitor
7
is effective at eliminating or reducing noise in the power supply VDD
6
and ground GND
5
.
It should be noted that the bypass capacitor
7
is localized with respect to the power supply VDD
6
, and therefore is effective. However, as stated above, prior and current techniques that are used to select the locations for the bypass capacitors do not always provide for such localization, and definitely do not ensure such localization. To the contrary, bypass capacitance locations are currently determined after the transistors, conductors, etc., have been laid out in a IC particular design. The locations for the bypass capacitors are selected as permitted by the design of the IC after the layout of many of the other components of the IC has been created. One of the disadvantages of this approach is that the bypass capacitors may end up being placed at locations where their ability to be effective is not optimized. As stated above, this generally is because the bypass capacitors are located too far away from the power supplies due to the lack of good locations from which to choose for the bypass capacitors. Another disadvantage of the current techniques for placing bypass capacitors in the IC is that current techniques do not optimize the use of spatial area on the IC.
Accordingly, a need exists for a technique that ensures localization of bypass capacitance so that noise in the power supply resulting from the aforementioned high frequency components can be minimized or eliminated.
SUMMARY OF THE INVENTION
The present invention provides for bypass capacitance localization in order to optimize the effectiveness of bypass capacitance at eliminating or reducing noise in the power supplies of an integrated circuit (IC). In accordance with the present invention, a determination is made as to which cells of macro cells of an IC have functionality that will actually be implemented during operations of the IC. Cells that have functionality that will not be used during the operations of the IC are identified as fill cells. At least a plurality of these fill cells are filled with bypass capacitors to ensure that there will be a sufficient amount of bypass capacitance in the IC to eliminate or reduce noise in the power supplies. Preferably most if not all of the identified fill cells are filled with bypass capacitors to ensure that the power supplies of the IC have bypass capacitors that are local to the power supplies of the IC. This ensures that noise in the power supplies will be eliminated or reduced by the effects of the bypass capacitors.
Because the fill cells exist on the IC, but are not a functional component of the IC, locating the bypass capacitors in these fill cells optimizes the use of space on the IC for bypass capacitors. Also, since there are typically many cells that will not be used once the data path block of macro cells has been constructed, by filling this large number of fill cells with bypass capacitors, it is virtually ensured that the power supplies of the IC will have bypass capacitors that are local to the power supplies, which ensures the effectiveness of the bypass capacitors without wasting real estate on the IC.
These and other features and advantages of the present invention will become apparent from the following description, drawings and claims.


REFERENCES:
patent: 6054751 (2000-04-01), Ichikawa et al.
patent: 6118169 (20

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