Bus transaction verification method

Details Bus transaction verification method Bus transaction verification method

2001-01-26

2004-01-27

Auve, Glenn A. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C702S118000, C703S014000, C703S024000

Reexamination Certificate

active

06684277

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to bus architectures, and more particularly to the verification of bus transactions for bus architectures.
BACKGROUND OF THE INVENTION
System-On-Silicon, Application Specific Integrated Circuit (ASIC), and other hardware which utilize standardized buses typically involve the simulation of logic designs which use bus transactions as defined by the bus architecture specifications. Bus models and other forms of test case stimulus are commonly used for bus transaction verification to ensure that the logic designs perform properly and are compliant with the bus architecture specifications.
In the process of bus transaction verification, each test case has a number of expected parameter values based on the bus architecture. These expected parameter values are compared with actual parameter values obtained from the bus verification process to verify the functioning of the logical components of the design. Conventionally, this bus transaction verification is performed either by hand-coding the expected parameter values into checking programs that check the actual signals on a per test case basis, or by visual inspection of the waveforms. The code and/or check parameter values and bus behavior are manually coded against the test case and architectural specification. This process is repeated for each test case. Thus, because manual coding is required, this process is cumbersome and time consuming. Also, there is significant chances of human error and inaccurate observation.
Accordingly, there is a need for an improved bus transaction verification method. The improved method should automate the coding of the check parameter values and the bus behavior against the test case and architectural specification. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and computer readable medium with program instructions for automatically verifying bus transactions. The method includes: parsing a parameter code for the bus transactions, wherein the parameter code comprises a plurality of expected parameter values for the bus transactions; automatically integrating the parsed parameter code into a checking program; and automatically executing the checking program, wherein the checking program compares the plurality of expected parameter values with a plurality of actual parameter values for the bus transactions. The bus transaction verification method in accordance with the present invention automates the coding of expected parameter values for each test case into a checking program and automates the execution of the checking program, where the checking program compares the expected parameter values with the actual parameter values. By automating the bus transaction verification in this manner, the process is more efficient and reduces the chances of human error and inaccurate observation.


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