Bus transaction accelerator for multi-clock systems

Details Bus transaction accelerator for multi-clock systems Bus transaction accelerator for multi-clock systems

1999-10-07

2003-06-24

Myers, Paul R. (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S061000, C713S501000

Reexamination Certificate

active

06584536

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to bus interface circuits and methods.
BACKGROUND: DEVICE COMMUNICATIONS
Technological advances have produced devices with increasing communication bandwidth requirements. Computers, digital cameras, printers, and scanners, for example, demand high speed communications to perform properly. Images and video signals require precise synchronization of communications in order to prevent jittery graphics due to lost frames or other synchronization problems. Each device will have its own internal clock. For communications between two devices, the clocks of both devices should be synchronized. This is normally done by bus transaction handshaking. Therefore, quick bus transaction handshaking becomes a critical part in developing fast device communication schemes.
A host system (such as a personal computer) may use bus transactions to communicate with an external system (such as a printer). The host system may send control commands or data to the external system via a control register. The external system may send data, interrupt requests, or system status information to the host system via a status register. Thus the status register may be used as an interrupt register to generate an interrupt and provide an indication as to the source of the interrupt.
Delays can arise when the external system and the host system use different clocks. When writing data to a register, there is a small amount of time when the data is not stable. A register that will contain a “1” after it has stabilized may be read as a “0” during this unstable period. If the data is read during this time, the results are unpredictable. Reliable data transfer requires synchronization between the clocks so that the systems will not read unstable data. Systems that communicate with control registers and status registers must be able to exchange stable data or communications may fail.
BACKGROUND: BUS TRANSACTION HANDSHAKING
One problem associated with communication between systems with different bus clocks is when to sample an incoming signal such that it can be read correctly. In a digital system, for example, reading the contents of a register before they have stabilized will have unpredictable results: a “1” may be read as a “0” or vice-versa. Accordingly, bus transactions are designed to eliminate the possibility of reading registers when they are in an unstable state. This commonly is accomplished through a process known as “handshaking.” Hand-shaking is exchange of a predetermined sequence of signals between two systems to establish synchronization between sending and receiving equipment for the purpose of exchanging data and status information.
An arrangement used to implement bus transaction handshaking is shown in
FIG. 22. A
host system
2200
incorporates an internal control holding register
2202
and an internal status register
2204
. The host system registers are clocked by a host system clock BCLK. An external system
2208
incorporates an internal control register
2206
and an internal status holding register
2210
. The external system registers are clocked by an external system clock NCLK. The host system puts control bits into control holding register
2202
. After a handshaking circuit enables control register
2206
, the contents of register
2202
are loaded into register
2206
. The contents of register
2206
may then be placed on a bus of system
2208
. Similarly, the external system
2208
may place status bits in the status holding register
2210
. After a handshaking circuit enables status register
2204
, the contents of register
2210
are loaded into register
2204
. The contents of register
2204
may then be placed on a bus of host system
2200
.
Conventional handshaking solutions provide low performance and low data throughput. A primary cause of the reduced performance and low throughput is the addition of bus cycles required to attain synchronization between the host system clock and the external system clock. Read and write transactions require synchronization between the host and the external system to meet stringent timing requirements. Additionally, synchronization of the request and response handshaking is also required between the host and external system. For example, bus cycles are lost waiting for the host bus request signal to become synchronized by the external system clock. Similarly, the response sent by the external system needs to be received under a synchronous environment with the host bus clock before the transaction may be completed. The host bus wastes bandwidth by essentially “standing by” while waiting for handshaking to become synchronized, when it could be sued to perform other transactions. When accessing status registers, there are at least two host bus clock cycles and three external system clock cycles which are wasted. With conventional handshaking each read transaction generally takes at least four host bus clock cycles+ three external clock cycles and each write transaction generally takes at least four host clock cycles+ three external clock cycles.
BACKGROUND: STATUS REGISTER ACCESS
FIG. 16
shows a prior art status register handshaking circuit. A flag_in bit from an external system enables an external system status register (flip-flop)
160
. When the register is clocked by the external system NCLK, a quasi-flag_in bit is loaded into the Q output of the register
160
. When handshaking circuitry enables flip-flop
162
, the next rising edge of NCLK will load the Q output of flip-flop
160
into the Q output of flip-flop
162
.
The handshaking circuitry incorporates a chain of flip-flops
164
,
166
,
168
,
170
,
172
, and
174
. The first flip-flop
164
is in a self-oscillating configuration with output Q-NOT connected to its input, D. A read request signal, rd_req, enables flip-flop
164
so that a next rising edge of host system clock BCLK will cause output Q to change states (from “1” to “0” or vice-versa). The Q output of flip-flop
164
is loaded into the Q output of flip-flop
166
at the next rising edge of NCLK. The Q output of flip-flop
166
propagates to the Q output of flip-flop
168
at the following rising edge of NCLK. At this point the Q output of flip-flop
168
will be different than the Q output of flip-flop
170
and the XNOR gate
178
will enable flip-flop
162
. At the next rising edge of NCLK, the Q output of flip-flop
168
propagates to the Q output of flip-flop
170
and the flag_bit propagates to the Q output of flip-flop
162
. At the following rising edge of BCLK, the Q output of flip-flop
170
propagates to the Q output of flip-flop
172
. At the next rising edge of BCLK, the Q output of flip-flop
172
is propagated to the Q output of flip-flop
174
. A XNOR gate
180
detects when the Q output of flip-flop
164
has propagated to the output of flip-flop
174
and places a logic “1” onto rd_response to signal the host system that flag_in has been successfully loaded into the Q output of flip-flop
162
. When using this scheme, the status read operation takes 4 BCLK+3 NCLK cycles before rd_response signals the operation is done.
FIG. 17
shows a timing diagram for the prior art circuit of FIG.
16
. For simplicity, BCLK and NCLK have the same frequency but are out of phase with each other. Note that the external system should not assert another flag_in until the rising edge of BCLK after rd_response is asserted. Thus status register updates are not available in increments of less than 4 BCLK+3 NCLK cycles.
BACKGROUND: CONTROL REGISTER ACCESS
FIG. 12
shows a prior art control register handshaking circuit. A Data_in bit vector is presented from the host system to a D input of an external system control register (flip-flop)
132
. When the register
132
is enabled by handshaking circuitry and clocked by the external system NCLK, the Data_in vector is loaded into the Q output of the register
132
.
The handshaking circuitry incorporates a chain of flip-flops
120
,
122
,
124
,
126
,
128
, and
130
. The first flip-flop
120

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