Bus-to-bus read prefetch logic for improving information transfe

Details Bus-to-bus read prefetch logic for improving information transfe Bus-to-bus read prefetch logic for improving information transfe

1995-06-07

1996-12-03

Harvey, Jack B.

395285, G06F 1300

Patent

active

055817149

ABSTRACT:
A method and system for improving bus-to-bus data transfers in a multi-bus computer system is provided. The system includes a system bus having a slave device attached thereto, a peripheral bus having a master device attached thereto, and a host bridge connecting the two buses. The system bus permits burst read transfers of data stored in the slave device, wherein a single address phase is followed by several data phases, but only if the first address corresponds to a prescribed system bus boundary. The peripheral bus is not subject to address boundary limitations, instead permitting burst read transfers beginning at any address. The host bridge includes logic for decoding a first address asserted by the master device to determine if it corresponds to a system bus boundary. If it does not, the logic commences a first read pre-fetch non-burst transfer of a first set of data stored in the slave device beginning at the first address and ending at a system bus boundary, and temporarily stores this first set of data in a buffer. The logic then commences a second read pre-fetch burst transfer of a second set of data stored in the slave device corresponding to data stored between system bus boundaries, and temporarily stores this second set of data in the buffer, so that both of the temporarily stored first and second sets of data may be read by the master device over the peripheral bus in a single burst read transfer.

REFERENCES:
patent: 5109494 (1992-04-01), Ehlig et al.
patent: 5255374 (1993-10-01), Aldereguia et al.
patent: 5315706 (1994-05-01), Thomson et al.
patent: 5392407 (1995-02-01), Heil et al.
patent: 5467295 (1995-11-01), Young et al.
Peripheral Component Inteconnect Revision 1.0 Jun. 22, 1992.

Affiliated with

Also associated with

Rating

Bus-to-bus read prefetch logic for improving information transfe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus-to-bus read prefetch logic for improving information transfe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus-to-bus read prefetch logic for improving information transfe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-794121