Bus-to-bus pacing logic for improving information transfers in a

Details Bus-to-bus pacing logic for improving information transfers in a Bus-to-bus pacing logic for improving information transfers in a

1995-06-07

1996-10-08

Harvey, Jack B.

395250, 395877, G06F 1300

Patent

active

055640265

ABSTRACT:
Hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.

REFERENCES:
patent: 5109494 (1992-04-01), Ehlig et al.
patent: 5255374 (1993-10-01), Aldereguia et al.
patent: 5315706 (1994-05-01), Thomson et al.
patent: 5353415 (1994-10-01), Wolford et al.
patent: 5369748 (1994-11-01), McFarland et al.
patent: 5455916 (1995-10-01), Bourke et al.

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