Bus-to-bus bridge for a multiple bus information handling system

Details Bus-to-bus bridge for a multiple bus information handling system Bus-to-bus bridge for a multiple bus information handling system

1993-05-28

1996-03-12

Harvey, Jack B.

Excavating

39518502, 371 491, G06F 1100

Patent

active

054993466

ABSTRACT:
An information processing system, comprising a central processing unit (CPU); a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; a second system bus connected to the CPU; a host bridge connecting the second system bus to a peripheral bus having at least one peripheral device attached thereto, the host bridge including register space for storing information related to transactions occurring over the peripheral bus; and error capture logic incorporated into the host bridge. The error capture logic monitors the transactions occurring over the peripheral bus, detects parity errors occurring during any of the transactions, and generates an interrupt routine over the second system bus to the CPU. The CPU reads the register space and performs necessary recovery operations.

REFERENCES:
patent: 4388684 (1983-06-01), Nibby, Jr. et al.
patent: 5155735 (1992-10-01), Nash et al.
patent: 5257391 (1993-10-01), DuLac et al.
patent: 5313627 (1994-05-01), Amini et al.

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