Bus termination scheme for flexible uni-processor and dual...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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Details

C326S086000, C326S090000, C710S100000

Reexamination Certificate

active

06522165

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of computer systems. More particularly, the present invention relates to the field of bus termination schemes.
2. Description of Related Art
Transmitting electrical signals over relatively long mismatched bus transmission lines between integrated circuit devices typically creates signal reflections. Signal reflections occur when only a portion of the power of a signal transmitted over a transmission line is output to the load at the end of the transmission line while the remaining portion of the power of the signal is reflected back onto the transmission line. The existence of signal reflections on transmission lines can result in overshoots, undershoots, and/or ringbacks, for example.
An overshoot typically occurs when the voltage of a received signal rises from a lower value, such as 0 Volts (V) for example, beyond a desired higher value, such as 3.3 Volts (V) for example, before settling near the higher value. An undershoot typically occurs when the voltage of a received signal falls from the higher value beyond the lower value before settling near the lower value. Ringbacks typically occur when a signal overshoot falls back below the higher value before settling near the higher value or when a signal undershoot rises back above the lower value before settling near the lower value.
Overshoots, undershoots, and ringbacks increase the amount of time required to read signals because the circuitry receiving each signal must wait relatively longer for the signal to settle near the higher or lower value prior to interpreting the signal as a logical one or zero, respectively. Because signals may be transmitted only as fast as they can be read, overshoots, undershoots, and ringbacks limit the frequency at which signals may be transmitted over a transmission line. Additionally, relatively large overshoots can damage circuitry designed to receive signals at voltage values of only some predetermined amount over the higher value.
To avoid or minimize signal reflections and therefore help maintain signal quality to allow signal transmission at relatively high frequencies, each transmission line may be terminated with a load having an impedance that is approximately equal to the characteristic impedance of the transmission line.
FIG. 1
illustrates a block diagram of a computer system
100
comprising a motherboard
102
, a first processor card
110
supporting a first processor
112
, a second processor card
120
supporting a second processor
122
, and a chipset
130
. Motherboard
102
has a processor bus formed by a plurality of transmission lines on motherboard
102
. One exemplary transmission line
104
is illustrated in FIG.
1
. Processor cards
110
and
120
are each mechanically and electrically coupled to the processor bus of motherboard
102
by insertion into a respective slot connector on motherboard
102
. Chipset
130
is mechanically and electrically coupled to motherboard
102
. At least one chip of chipset
130
is mechanically and electrically coupled to the processor bus of motherboard
102
.
Processor
112
comprises on-die terminating pull-up resistors at or near the end of each transmission line at processor
112
. Processor
122
comprises on-die terminating pull-up resistors at or near the end of each transmission line at processor
122
. The terminating resistors each have an impedance approximately equal to the characteristic impedance of its corresponding transmission line to help avoid or minimize signal reflections at processors
112
and
122
. As one example, processor
112
comprises an on-die terminating pull-up resistor
116
at or near its end of transmission line
104
, and processor
122
comprises an on-die terminating resistor
126
at or near its end of transmission line
104
.
The end of each transmission line at chipset
130
is not terminated with a resistor to help reduce design complexity and power dissipation that results from constant current flow through terminating resistors as a result of driving either end of each transmission line low. Because this single-ended termination scheme produces signal reflections at the end of each transmission line at chipset
130
, the length of each stub for chipset
130
, such as stub
134
for example, is relatively short to help minimize such signal reflections.
Computer system
100
may be changed to a uni-processor system by removing processor card
120
, for example, from its slot connector on motherboard
102
. Because the end of each transmission line at that slot connector would no longer have terminating resistors following removal of processor card
120
, a bus termination card comprising terminating resistors for each such transmission line is typically inserted into the slot connector to avoid or minimize signal reflections. One or more resistors of a bus termination card, however, may not be firmly coupled to bus termination card and/or may become loose, for example, from rough handling by a user. As a result, one or more transmission lines may not be terminated by the bus termination card. A bus termination card also incurs an added expense for computer system
100
.


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patent: 6026456 (2000-05-01), Ilkbahar
patent: 6122695 (2000-09-01), Cronin
patent: 6204683 (2001-03-01), Falconer
patent: 6218863 (2001-04-01), Hsu et al.
patent: 6229335 (2001-05-01), Huang et al.
patent: 6232814 (2001-05-01), Douglas, III
patent: 6249142 (2001-06-01), Hall et al.
100 MHz GTL + Layout Guidelines for the Pentium® II Processor and Intel 440BX AGPset, Intel Corporation, Application Note AP-827, 1997.
Slot 1 Bus Termination Card Design Guidelines, Intel Corporation, Aug. 1997.
Intel® 440BX AGPset Design Guide, Intel Corporation, Apr. 1998.
Intel 100MHz Pentium® II Processor/440GX AGPset Dual-Processor Customer Reference Schematics (Revision 1.0), Intel Corporation, Oct. 30, 1998.
100 MHz AGTL + Layout Guidelines for the Pentium® III Processor and Intel® 440BX AGPset, Intel Corporation, Application Note AP-906, Feb. 1999.
Intel® 440GX AGPset Design Guide, Intel Corporation, Mar. 1999.
SC242 Termination Card Design Guidelines, Intel Corporation, Nov. 1999.
Pentium® III Processor for the SC242 at 450 MHz to 1.13 GHz Datasheet, Intel Corporation, Jul. 2000.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz Datasheet, Intel Corporation, Oct. 2000.

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