Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2008-07-08
2008-07-08
Auve, Glenn A (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
11543878
ABSTRACT:
A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
REFERENCES:
patent: 4016546 (1977-04-01), Bennett et al.
patent: 4439829 (1984-03-01), Tsiang
patent: 4665483 (1987-05-01), Ciacci et al.
patent: 4695944 (1987-09-01), Zandveld et al.
patent: 4700348 (1987-10-01), Ise et al.
patent: 4780813 (1988-10-01), Gierety
patent: 4851990 (1989-07-01), Johnson et al.
patent: 4945267 (1990-07-01), Galbraith
patent: 4945540 (1990-07-01), Kaneko
patent: 4982321 (1991-01-01), Pantry et al.
patent: 5003465 (1991-03-01), Chisholm et al.
patent: 5274795 (1993-12-01), Vachon
patent: 5359715 (1994-10-01), Heil et al.
patent: 5483642 (1996-01-01), Okazawa et al.
patent: 5506973 (1996-04-01), Okazawa et al.
patent: 5668956 (1997-09-01), Okazawa et al.
patent: 5751976 (1998-05-01), Okazawa et al.
patent: 5889971 (1999-03-01), Okazawa et al.
patent: 5935231 (1999-08-01), Okazawa et al.
patent: 6006302 (1999-12-01), Okazawa et al.
patent: 6098136 (2000-08-01), Okazawa et al.
patent: 6195719 (2001-02-01), Okazawa et al.
patent: 6334164 (2001-12-01), Okazawa et al.
patent: 6810461 (2004-10-01), Okazawa et al.
patent: 6907489 (2005-06-01), Okazawa et al.
patent: 7152130 (2006-12-01), Okazawa et al.
patent: 141302 (1985-05-01), None
patent: 191939 (1986-08-01), None
patent: 63-47864 (1988-02-01), None
patent: 1-106255 (1989-04-01), None
patent: 1-134652 (1989-05-01), None
patent: 02-128250 (1990-05-01), None
Glass, “Inside EISA”, Byte, vol. 14, No. 12, Nov. 1989, pp. 417-425.
Baran, “EISA Arrives”, Byte, vol. 14, No. 12, Nov. 1989, pp. 93-98.
“The Surging RISC”, Nikkei Electronics, No. 474, May 29, 1989, pp. 106-119.
Aburano Ichiharu
Kawaguchi Hitoshi
Kimura Koichi
Kobayashi Kazushi
Mochida Tetsuya
Auve Glenn A
Hitachi , Ltd.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
LandOfFree
Bus system for use with information processing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bus system for use with information processing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus system for use with information processing apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3936152