Bus system for shadowing registers

Details Bus system for shadowing registers Bus system for shadowing registers

1998-03-06

2001-06-12

Wiley, David A (Department: 2155)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

Reexamination Certificate

active

06247087

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to updating information shared between one or more bus devices in a computer system, and more particularly, to a system for shadowing registers of these devices.
2. Description of the Related Art
Personal computers are constantly evolving to provide the user with the highest performance available at the lowest cost. Performance improvements in the microprocessor and memory systems have resulted in computers so powerful that they are now capable of performing tasks that before could only be performed by large mainframe computers. Technological change is especially exemplified in the area of portable computers where power consumption efficiency is balanced against features, cost, size, weight and performance. Achieving this balance is especially challenging since many computer users demand the portable computer to provide nothing less than what a desktop unit can provide. The term “portable computers” is used broadly here to denote the class of computers powered by battery or solar power. Those familiar with portable computers will recognize labels such as portable, luggable, laptop, notebook and handheld, which are used to designate certain marketing segments of the larger portable computer market.
Many options are available to the computer system designer. While designing around the highest performance processor available will go far towards providing a high performance product, in today's competitive market that is not enough. The processor must be supported by high performance components, including a high performance expansion bus. Several standardized expansion buses are available to the system designer, including the ISA (Industry Standard Architecture) bus and the EISA (Extended Industry Standard Architecture) bus.
For the system bus, a high performance bus such as the Peripheral Component Interconnect (PCI) bus or the EISA bus is used. The three above-described buses are familiar to those skilled in the art.
Design choices also involve implementing certain special features of the computer that distinguish one manufacturer's computer from a competitor's. In the portable computer market this is especially challenging since added features can cause increased size and weight. For example, since software can require large amounts of storage, a high capacity hard disk drive is often desirable. However, such high capacity disk drives are usually larger and heavier than desirable for a portable computer. It is also desirable to have the ability to add functionality to the portable computer using expansion hardware. However, providing integral expansion bays compromises the small size.
One known method of providing additional features without sacrificing size and weight is through the use of an expansion base unit. An expansion base unit is a non-portable unit that typically operates from AC power and resides on a user's desktop. When the user is working at the desk, the portable computer plugs into the expansion base unit, which then provides the added functionality. The expansion base unit may include a network interface unit for connecting to a local area network, one or more high capacity disk drives, a floppy drive and other peripherals.
Typically, in a computer system having a laptop computer unit and an expansion base unit, information regarding floppy disk drive selects, motor selects and status bits are stored in floppy disk drive control registers. Such a computer system, however, may have two sets of these registers, one set located in a floppy drive controller of the laptop unit and one set located in a floppy drive controller of the expansion base unit. To ensure system compatibility the floppy disk drive registers of the laptop unit would typically have the same address as the corresponding registers of the expansion base unit.
Thus, these bus devices must have various registers that share common data. A problem occurs when the data in one of these registers is updated because registers sharing the same address should contain the same data.
Reflecting the contents of one register in another register is known as “shadowing.” Data in a “shadowed” register is shadowed by one or more “shadowing” registers. One way to shadow a register is to perform bus write operations to every shadowing register when the shadowed register is updated with new data. However, as noted above, both the shadowed and the shadowing floppy disk drive registers should share a common address. The data is transferred to each set of floppy drive registers through an associated bridge circuit. Therefore, a problem arises in writing to both sets of floppy drive registers as the bridge circuits may not concurrently be able to transfer the data to the registers.
SUMMARY OF THE INVENTION
Briefly, the present invention relates to a system for shadowing write operations to a first register of a first bus device in a second register of a second bus device. Both the first and second registers share a common address and are accessible through a system bus. A first bridge circuit coupled to the system bus controls write operations to the first register, and a second bridge circuit coupled to the system bus controls write operations to the second register.
The first bridge circuit includes positive decode logic to detect a first write operation to the first register from a bus agent of the system bus. Upon positively decoding such a write, the retry logic interacts with first slave logic to furnish a known retry sequence on the system bus. This aborts the first write operation which must then be retried. An arbiter of the first bridge circuit masks a system bus request from the bus agent which attempts to retry the first write operation.
A retry bus master of the first bridge circuit then performs a second write operation over the system bus to the common address using the same data and address of the first write operation. This allows second slave logic of the second bridge circuit to subtractively decode and accept the write operation. When this occurs, the second bridge circuit transfers the data to the second register.
After the second write operation, the retry logic interacts with the arbiter to unmask the system bus request from the bus agent. This allows the arbiter to grant the system bus to the bus agent. The bus agent can then retry the first write operation. This allows the first slave logic to positively decode and accept the retried first write operation. Upon this occurrence, the first bridge circuit transfers the data to the first register. Thus, updates in the register data are reflected, or shadowed, to all registers sharing the common address.


REFERENCES:
patent: 5640570 (1997-06-01), St. Clair et al.
patent: 5642489 (1997-06-01), Bland et al.
patent: 5903766 (1999-05-01), Walker et al.
patent: 5943507 (1999-08-01), Cornish et al.
DMA Support on the “PCIway”, Aug. 2, 1995, Version 5.4, Preliminary,pp. 2-16.
PCI Specification, Rev. 2.1, A100910, pp. 37-72, Aug. 3, 1995.

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