Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-11-24
2004-06-29
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S243000, C712S028000, C712S225000
Reexamination Certificate
active
06757766
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a bus for a highly scalable multiprocessor system and to a redundant bus system that uses this bus, as well as to a method for transmitting information in the redundant bus system.
FIG. 1
is a block illustration of a bus system known in the prior art. The bus
3
typically includes an address bus
4
, a data bus
5
and a control bus
6
. Connected to the bus
3
are several central units
2
and a memory storage device
1
. Within the memory storage device
1
are submemories A and B. Several central units
2
maybe connected to the bus
3
, such as central units A and B, for example, as shown in FIG.
1
. The common bus
3
allows the central units access to the memory storage unit
1
and submemories A and B, in particular.
FIGS. 2A and 2B
are a schematic illustration of a conventional read and write process in a conventional bus system as depicted in FIG.
1
.
FIG. 2A
illustrates a read process. Typically, the respective memory addresses from an address register of a central unit
2
are first accessed, the address being increased after each transfer until the desired number data items is transmitted. Access of the memory addresses is accomplished via the address bus
4
. Subsequently, control signals, for instance a request signal and read/write signals, are generated by the central unit
2
. These control signals are transmitted to the memory
1
via the control bus
6
. The central unit
2
then waits until the memory
1
sends back a ready flag via the control bus
6
. Data can then be read from the memory
1
under the respective address.
FIG. 2B
is a schematic illustration of writing into the memory
1
. Writing functions in a manner similar to the above described read process.
FIG. 3
is a schematic illustration of a conventional command cycle. As illustrated in
FIG. 3
, a command cycle as processed in the bus system according to
FIG. 1
consists of an address phase A
1
, a collect command phase B
2
and an execute phase C
3
. In the conventional bus system an address is first delivered to the storage device
1
in the address phase A
1
. In the collect command phase B
2
, the storage device
1
allows the data word at the addressed memory space to be accessed. The data word can then be read and collected by the central unit
2
via the data bus
5
. In the execute phase C
3
, data that have been read from the storage device
1
are processed.
The conventional bus structure described above has the disadvantage that for highly scalable multiprocessor systems, in particular, (i.e., bus systems comprising a flexibly expandable number of central units
2
) the data transmission via the bus is insufficient since the plurality of central units causes a high number of bus accesses. Particularly in communication systems that require power to be adjustable up to approximately a power of ten due to the addition of processors, conventional bus systems with a unified bus lead to significant complications. It is also necessary that individual hardware errors must not lead to failure of the system. Thus a redundant system is required. However, such redundancy requirements necessitate an extraordinarily high wiring outlay with the conventional bus system, in addition to causing transit time problems and less flexible circuit arrangements. In order to guarantee compatibility with existing software, a large shared memory for all processors must be utilized. This shared memory must then be doubled in order to be available logically to accommodate errors in the memory system.
Typically, a conventional highly scalable multiprocessor system is realized with a spatially distributed bus system, wherein each processor is connected to both redundant memory halves A and B via specific bus subassemblies and cable lengths. Besides the previously mentioned transit time problems, development costs for the bus subassemblies is considerable, causing high production costs as well as an extraordinary space requirement in the stand or rack of the system.
FIG. 4
is a schematic illustration of a conventional bus with the address bus
4
, the data bus
5
and the control bus
6
. As depicted in
FIG. 4
, the address bus
4
consists of a plurality of address lines. Similarly, the data bus
5
can consist of a plurality of data lines that respectively comprise the width of one data word. As illustrated in
FIG. 4
, the control bus
6
consists of an access control line or arbitration line, as well as a command line and a line for transmitting a ready flag.
During a read cycle as illustrated in
FIG. 4
, an address is first applied at the address bus
4
during cycle
1
(i.e., from time t=0 to time t=1). During the subsequent cycle
2
, the access rights are requested on the arbitration line and the read command is transmitted on the command line of the-control bus
6
. The central unit now waits for the ready flag of the memory
1
until it is indicated on the ready flag transmitting line of the control bus
6
during cycle
6
, for example. The data can be subsequently read out via the data bus
5
during cycles
7
to
10
.
A write cycle follows in a similar manner, also illustrated in FIG.
4
. An address to be written is applied at the address bus
4
in cycle
11
, whereupon access rights on the arbitration line and the write command are controlled via the control bus
6
during cycle
12
. The ready flag then occurs relatively quickly, for instance in cycle
13
. The data can then be written into the memory
1
via the data bus
5
during cycles
14
to
16
. However, as illustrated in
FIG. 4
, the holding time of the bus is extraordinarily high due to the long wait times. This leads to considerable problems particularly when, instead of the customary “burst” accesses in which block transfers occur via the bus, individual accesses are carried out, as is the rule in communication systems, for example. Thus, given a plurality of individual accesses, high bus holding times arise in the prior art, though only a small volume of data is transmitted.
SUMMARY OF THE INVENTION
Therefore, a need exists to create a bus for a highly scalable multiprocessor system, a redundant bus system that uses this bus, and a method for transmitting information on such a bus system, wherein the bus holding times and latencies are reduced and a simple and cost-effective hardware realization is possible.
The above needs are met by the present invention which features a bus and bus system including an address bus having at least one address access control line and at least one address identifier line. Further, a data bus is included that has at least one data bus access control line and at least one data identifier line. The at least one address and data access control lines control the right to access the address and data buses. In addition, the at least one address and data identifier line transmit an identifier that enables allocation of address information to pertinent data information. The featured bus may also be included in a bus system having two or more of the featured buses, thereby creating a redundant bus system.
In particular, the use of a chronologically divided address and data bus that respectively comprise access control lines and identifier lines, wherein the identifier lines transmit an identifier for the allocation of the address information to the data information, results in a bus that can perform data transfers chronologically independent of address requests and, thus, sharply reduce the bus holding times particularly during individual accessing of the bus.
The divided address and data bus preferably has check sum lines for transmitting a check sum of the signals transmitted on the bus, as well as acknowledgment lines for transmitting an acknowledgment signal corresponding to a signal for comparing the signals that are transmitted via the respective bus to the check sum. A secure transmission is thus obtained on each bus.
The address bus additionally comprises command lines for transmitting a command, which is preferably a writ
Hutner Franz
Peleska Pavel
Morrison & Foerster / LLP
Myers Paul R.
Phan Raymond N.
Siemens Aktiengesellschaft
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