Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-01-31
2004-08-24
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S006000, C710S310000
Reexamination Certificate
active
06782439
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus system and execution scheduling method for access commands thereof, and more particularly, to a bus system including a plurality of slave devices, in which commands issued by master devices are executed by slave devices in the order in which an execution preparation is made, and an execution scheduling method thereof. The present application is based on Korean Patent Application No. 2000-42000 filed on Jul. 21, 2000, which is incorporated herein by reference.
2. Description of the Related Art
A bus master is a system module that is able to initiate read and write operations by providing address and control information. A bus slave is a system module that responds to a read or write operation within a given address-space range. Representative examples of master and slave devices are processors and memories. A master device and a slave device communicate with each other through a bus. In other words, a command from the master device are transmitted to the slave device, and execution of the transmitted command is completed by transmitting predetermined data from the slave device to the master device or from the master device to the slave device.
In order for a plurality of master devices to use a common bus fairly and effectively, various conventional arbitration methods have been developed and applied. However, conventional arbitration methods involve arbitrating ownership of an address/control bus and a data bus. In other words, a bus arbiter only serves to arbitrate ownership of a bus, and a master device, at that point, has the authority to control and use the bus. Thus, if ownership of a data bus and address/control buses is given to a specific master device according to an arbitration algorithm, the master device exclusively owns the data bus and address/control bus until the execution of commands is complete.
Accordingly, if a command transmitted to a slave device that is connected to various local data buses, the transfer bandwidth of which is narrower than a main data bus, such as an input/output (I/O) bus connected to an I/O device and a ROM bus coupled to a boot ROM, is to be executed, the main data bus lies idle during some clock cycles. This is because the main data bus is monopolized by a master device issuing a command until data to be transferred passes through the local data bus, which is slower than the main data bus in data transfer, i.e., execution of the command is completed. In the case of a write command in which data is transferred from a main data bus to a local data bus, idle clock cycles of the main data bus can be reduced by keeping data in a bridge device provided between the main data bus and the local data bus and completing monopoly of the main data bus by the master device. However, in the case of a read command in which data must be transferred to the master device through the main data bus, the master device needs to wait with the main data bus lying idle, until the data transferred from the local data bus is delivered to the main data bus. Accordingly, the operational speed of the overall system is reduced by a large number of idle clock cycles of the main data bus.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a bus system having an improved data transfer speed by scheduling the execution of commands using an execution scheduling method for the bus system.
Accordingly, to achieve the above objective, the present invention provides a method of scheduling execution of access commands including the steps of (a) transmitting one or more access commands issuing from one or more master devices to corresponding slave devices, (b) storing the transmitted access commands, and (c) the slave devices executing the stored access commands in the order in which execution preparation of the access commands is completed. The step (a) preferably includes the steps of (a1) temporarily storing the access commands, and (a2) transmitting the stored access commands to the corresponding slave devices on a first-in-first-out (FIFO) basis. The step (c) includes the steps of: (c1) receiving a notice indicating that the execution preparation is completed from the slave device, and (c2) sending instructions to the corresponding slave device to begin execution of the access command. In this case, the access command issuing from the master device is transmitted from a predetermined arbiter as a result of arbitration.
The present invention also provides a bus system including an arbiter for outputting one or more access commands from one or more master devices in an order according to a predetermined arbitration result, and an execution scheduler granting a data bus to slave devices corresponding to the access commands output from the arbiter so that the access commands may be executed in the order in which execution preparation of the access commands is completed. The execution scheduler preferably includes an access command distribution unit for receiving the access commands output from the arbiter and transmitting the access commands to the corresponding slave devices, and an execution scheduling unit for transferring an execution starting signal of the transmitted access command to a slave device, which has sent an execution preparation completion signal and has received the access commands from the access command distribution unit.
The slave device preferably includes an execution command storing unit for storing the access command transmitted from the execution scheduler, and an execution unit for transmitting the execution preparation completion signal to the execution scheduler, executing the access command stored in the execution command storing unit if the execution starting signal is received, and transferring an execution completion signal to the execution scheduling unit if the execution is completed.
Preferably, the access command distribution unit includes the command storing unit for storing the access command received from the arbiter, and the command storing unit includes a command storage queue for storing the access commands and a command storage queue controller for controlling the command storage queue.
The execution scheduling unit preferably includes an identifier storage queue including one or more storage cells for storing an identifier of a corresponding slave device, which receives the access command through the access command distribution unit, an identifier storage queue controller for controlling the identifier storage queue, comparators, each of which corresponds to a respective storage cell, for determining whether or not an identifier stored in the storage cell is the same as an identifier of the slave device transmitting the execution preparation completion signal, and a decoder for transmitting the execution starting signal to the slave device, which transmits the execution preparation completion signal, if both identifiers are determined to be the same by the comparator.
The execution command storage unit preferably includes an execution command storage queue for storing the access commands, and an execution command storage queue controller for controlling the execution command storage queue.
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